IBIS Macromodel Task Group

Meeting date: 21 December 2010

Members (asterisk for those attending):
Agilent:                    * Fangyi Rao
                              Radek Biernacki
Ansoft:                       Chris Herrick
                              Danil Kirsanov
Ansys:                      * Samuel Mertens
                            * Dan Dvorjak
                              Deepak Ramaswamy
                              Jianhua Gu
Cadence Design Systems:       Terry Jernberg
                              Ambrish Varma
Celsionix:                    Kellee Crisafulli
Cisco Systems:              * Mike LaBonte
                              Stephen Scearce
			      Ashwin Vasudevan
Ericsson:                     Anders Ekholm
IBM:                          Greg Edlund
Intel:                      * Michael Mirmak
LSI Logic:                    Wenyi Jin
Mentor Graphics:            * John Angulo
                              Vladimir Dmitriev-Zdorov
                              Zhen Mu
                            * Arpad Muranyi
Micron Technology:            Randy Wolff
Nokia-Siemens Networks:     * Eckhard Lenski
Sigrity:                      Brad Brim
                              Kumar Keshavan
                              Ken Willis
SiSoft:                     * Walter Katz
                              Mike Steinberger
                            * Todd Westerhoff
ST Micro:                     Syed Sadeghi
Teraspeed Consulting Group: * Scott McMorrow
                            * Bob Ross
TI:                           Casey Morrison
                              Alfred Chong
Vitesse Semiconductor:        Eric Sweetman
Xilinx:                       Mustansir Fanaswalla

The meeting was lead by Arpad Muranyi

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Opens:

- Arpad said the next meeting would be Jan 4, 2011

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Call for patent disclosure:

- none

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Review of ARs:

- Walter submit BIRD to open forum
  - Done

- Arpad update and distribute Defaults BIRD
  - Done
  - BIRD 126 now

- Walter send example SPICE deck to Mike for posting
  - Done

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New Discussion:

Arpad showed the Typos BIRD
- Arpad read passages from the BIRD related to input and output strings
- Page 5:
  - Bob: Is the Usage passed to the DLL?
    - Is it prohibited?
  - Walter: It should be prohibited
  - Mike: List based formats like this allow for extraneous content
    - Programs pick what they want, ignore all else
  - Bob: We may be using "leaf" ambiguously here
  - Arpad: All leaves have to begin with one of these keywords
- Arpad: Are we ready to vote on this?
- Bob: We should vote in January

Arpad showed BIRDs 123 & 124:
- Walter: Bird 123 is the "jitter" BIRD
  - We did not understand this well 3 years ago
  - This redefines how jitter is described to the EDA tool
  - Only Tx_DCD is reused, with clarification
  - DCD is important
    - a 6GHz signal often has a 3GHz clock
      - Clock DCD is introduced
  - Pulse width distortion is a data artifact
  - Rj is just random, Gaussian
    - Might be caused by using multiple internal data paths of different lengths
  - Sj is sinusoidal
    - Might be power supply fluctuation
- Arpad: The Usage of these is Info
  - What is the meaning of how this should be used?
- Walter: 
  - The tool could use it for statistical processing
  - Jitter may come form the model itself
    - In that case it would be Out
- Arpad: How can it influence the jitter
- Walter: The Out is from the Init call
- Arpad: That should be in the text
- Walter: Agree
- Bob: Do we disallow Corner for Out parameters?
- Walter: That should not be allowed
- Walter: Note there is no Dj here
  - That is pattern dependent
  - It would have to be handled by GetWave
- Michael M: This means the tool is doing most jitter calculation
  - The model author does not control the calculation
- Walter: FUJ is Founded Uncorrelated Jitter
  - Did not add a parameter for this
  - Could using existing Tx_Jitter keyword with tables
- Fangyi: This sounds related to Rj and Dj

- Walter: Rx is very different
  - Rx has 2 clocks: system and recovered
  - The recovered clock interacts with both data and the system clock
  - An Init-only model can use only parameters for clock recovery
  - There is no Rx_Clock_Recovery_Sj frequency
  - If no Tx clock ticks the params are used
    - Otherwise params not used
- Scott: A flow diagram would help here
  - All tools must give the same results
- Walter: Agree
- Walter: Jitter is in units of time
  - Rx_Noise is amplitude
- Fangyi: If Rx GetWave returns clock ticks does EDA tool use these
  parameters?
- Walter: Yes it could, the jitter may be on the system clock
  - This is in addition to the jitter from Rx GetWave
- Scott: GetWave can use these as inputs
  - It will impact clock ticks coming out
  - There are 3 choices for jitter:
    - 1 Completely model it inside Rx
    - 2 GetWave perturbs the signal
    - 3 Pass parameters to the EDA tool to handle it
- Walter: It could be Model_Specific too
- Arpad: Is there any ambiguity here?
- Walter: We need to look at that carefully
- Bob: Tx DCD is the only one that allows Corner
  - Should it also have List?
- Walter: It should, and the others should have the same rules
  - List is not that logical, but it could be allowed
  - Value, Range, and Corner should do it
  - The BIRD is mostly consistent with 5.0

BIRD 124:
- Walter: Dependency format defined
  - Tx_Strength_Table is used as an example
  - This provides "knobs" for users to control
  - It helps to have setting one parameter change others too
  - Would have dependent and independent parameters

Arpad thanked everyone for a year of good work on AMI

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Next meeting: 4 Jan 2011 12:00pm PT

Next agenda:
1) BIRD 121-124 discussions

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IBIS Interconnect SPICE Wish List:

1) Simulator directives

